This invention relates to data processing systems, and more particularly to those systems which include a plurality of devices that communicate over a single parallel data bus in time-shared fashion. Clearly, one basic constraint which such systems must meet is to insure that only one device transmits on the bus at a time. Otherwise, if this constraint is not met, the data on the bus will be garbled.
In the prior art, a variety of circuits have been disclosed which implement the time-sharing function. But typically, those circuits operate in a synchronous fashion, whereby the decision of which device may use the bus is made by sampling "request" signals from the devices with clock pulses of a predetermined frequency. By comparison, in the disclosed data processing system, the allocation of the bus is made without the use of clock pulses in totally asynchronous manner.
Also in the prior art, the circuits which implement the time-sharing function typically are constructed as a single integrated unit which can control only a predetermined maximum number of devices. By comparison, in the disclosed data processing system, allocation of the bus is performed by circuits called arbiters and selectors which are completely modular, and which can readily be interconnected to allocate any number of devices to the bus.
Accordingly, it is a primary object of the invention to provide a novel data processing system wherein transmissions by a plurality of devices over a single data bus are controlled with modular networks of asynchronous arbiters and selectors.